As known, the provision of non-volatile memory matrixes of the so-called EPROM and flash type has proved to have relatively low yields. The prior art has sought to remedy the low yield of the production process of flash memories. The solution thus far adopted consists of equipping the cell matrix with additional rows and/or columns--termed redundant--which could be used if necessary to replace rows or columns which prove defective or display malfunctions after testing of the device.
Those skilled in the art know well the design methodologies using redundant rows and columns and the associated selection circuitry. The latter allows readdressing the memory in such a manner as to replace the addresses containing defective bits with operating ones present in the redundant rows or columns.
Currently, the continuing evolution of technology and the market trend for semiconductors lead to designing memory devices capable of operating with ever lower supply voltages. This involves several significant problems due to the fact that to obtain a memory device efficient and fast in response, in particular in the reading phase, it is necessary that the redundant cells and circuitry meet certain stringent specifications. In particular, the UPROM memory cells incorporated in the selection circuitry, and which contain the binary codes of the addresses to be redundant, must be able to operate effectively even with low power supply.
In FIG. 1 is shown the basic structure of a UPROM memory cell 2 connected between a first reference power supply voltage Vcc and a second reference voltage GND, e.g. a signal ground. This UPROM comprises a memory element represented by a floating gate cell FC of the EPROM or flash type containing a binary code of an address to be redundant. This cell FC has a conduction terminal, the source terminal, directly connected to ground while another conduction terminal (drain) is connected to the power supply Vcc through a complementary pair of MOS transistors M1, M2. The basic structure of the UPROM cell 2 also comprises a first inverter I1 and a second inverter I2 each having its respective input and output terminals connected to the output and the input of the other inverter.
The first MOS transistor M1 of this complementary pair is the P-channel type and connects the input of the first inverter I1 with the power supply Vcc. The second MOS transistor M2 is the N-channel type and connects the input of the first inverter I1 with the drain terminal of the cell FC in a source follower configuration.
The control terminal of the cell FC receives a signal UGV, while to the respective control terminals G1 and G2 of the transistors M1 and M2 is applied a signal POR# and a biasing voltage signal Vb. The signal POR# represents the negated form of a power on reset signal POR. The signal POR is applied to the control terminal G3 of an enablement transistor M3 inserted between the output of the first inverter I1 and ground GND. The inverters I1 and I2 make up a register of the latch type and the transistors M1, M2 and M3 allow performance of the initialization phase of this latch.
The cell FC is programmed in the test phase, i.e. at the moment the memory devices are subjected to an Electrical Wafer Sort (EWS). Before performing any kind of operation on the memory device, the FC cells of the UPROM circuitry are read and will permit correct addressing of the memory addresses to be replaced. To be able to perform the reading it is necessary to appropriately bias the terminals of the FC cell.
Operating at low supply voltages Vcc near 2 V there arise problems for generating and managing the signals necessary for performance of the above mentioned biasing phase. The technical problem underlying the present invention is a UPROM biasing circuit cell having structural and functional characteristics such as to allow fast reading of the memory element of the UPROM cell while being able to operate with low supply voltage. This would allow overcoming the limitations and shortcomings of the present solutions proposed by the prior art for low voltage memory devices.